SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
SCALE uses self-supervised layout text generation and rule-guided sampling to boost sub-2nm local DRV fixing accuracy up to 97%.
Key Findings
Methodology
This work introduces a self-supervised framework where multi-layer geometries are serialized into structured text, training autoregressive models to reconstruct masked polygons from BEOL context without labels. During inference, natural language rules and high-temperature sampling generate diverse violation-prone layouts, validated by industrial DRC tools, producing annotated layout-violation pairs for fine-tuning a rule-aware DRC-VLM. The process involves: • serialization of multi-layer geometries; • self-supervised masked polygon prediction; • rule-conditioned diverse layout sampling; • industrial DRC validation; • fine-tuning DRC-VLM; • AI-guided local repair. This approach addresses complex conditional rules and dense multi-layer routing challenges in advanced nodes.
Key Results
- On 100 real sub-2nm cases, the proposed method improves local DRV fix success rates by 12-25%, reaching up to 97%. It significantly enhances repair effectiveness across enclosure, spacing, width, and color-spacing violations, outperforming baseline methods. The generated layout diversity and rule coverage surpass existing models, demonstrating robustness in complex environments.
- The proposed autoregressive generator achieved an entropy of 5.07, producing 289 unique topologies and triggering 29 VIA and 34 metal rule types, outperforming diffusion and script baselines. Fine-tuned DRC-VLM achieved rule F1 of 61.6% and localization F1 of 44.2%, significantly better than Gemini-3-Pro and GPT-5.2, confirming its superior spatial reasoning and rule understanding.
- In ablation studies, natural language guidance and multi-layer serialization proved essential for high rule coverage and diversity, validating the framework’s effectiveness in complex, condition-dependent layout violations.
Significance
This research bridges the gap between visual layout understanding and rule-based verification, enabling fully automated, intelligent local DRV fixing at advanced nodes. It combines deep learning with industrial validation, offering a scalable solution to the escalating complexity of semiconductor design rules. The framework enhances design automation, reduces manual effort, and improves reliability, pushing the industry toward higher density, more complex chip manufacturing with reduced costs and faster turnaround.
Technical Contribution
Key innovations include: • a self-supervised multi-layer layout serialization method enabling geometric understanding; • natural language conditioned sampling for diverse violation generation; • rule-aware fine-tuning of vision-language models for root-cause analysis; • integration with industrial DRC tools for automatic violation annotation and repair guidance. Unlike template-based or single-layer approaches, this framework provides an end-to-end deep learning solution capable of handling complex, conditional, multi-layer geometries with high fidelity.
Novelty
This work is the first to leverage self-supervised text-based serialization of multi-layer layouts combined with natural language rule conditioning to generate violation-prone layout variants. It introduces a rule-aware VLM fine-tuned on industrial data, enabling accurate violation root cause analysis and repair guidance, surpassing prior template or image-based methods in complexity handling and diversity.
Limitations
- The model may struggle with extremely dense, overlapping geometries or ambiguous rule boundaries, leading to potential missed violations or incorrect fixes.
- Training requires extensive real layout and DRC validation data, which is costly and may limit generalization across different process nodes or rule sets.
- High-temperature sampling increases diversity but can produce low-quality or irrelevant layouts, necessitating further optimization of sampling strategies.
Future Work
Future directions include integrating reinforcement learning to optimize violation generation and repair strategies, expanding model applicability to various process nodes, and exploring multi-modal inputs combining images and text for enhanced spatial reasoning. Additionally, reducing data dependency and improving robustness in extreme layouts remain key challenges.
AI Executive Summary
As semiconductor technology advances toward sub-2nm nodes, the complexity of layout design rules and dense multi-layer routing geometries pose significant challenges for local place-and-route (P&R) violation fixing. Traditional rule-based methods struggle to keep pace with the increasing conditionality and density of design constraints, often requiring manual intervention that hampers efficiency and reliability.
In response, this study introduces SCALE, a novel framework that leverages deep learning and self-supervised generation to automate the detection and correction of design rule violations. The core innovation lies in serializing multi-layer geometries into structured text, enabling the training of autoregressive models to reconstruct masked polygons from BEOL context alone. During inference, natural language rule constraints and high-temperature sampling steer the generation toward violation-prone layouts, which are then validated by industrial DRC tools. The resulting annotated layout-violation pairs are used to fine-tune a domain-adapted vision-language model (DRC-VLM) capable of rule-aware geometric reasoning.
Extensive experiments on 100 real sub-2nm layouts demonstrate that the proposed approach boosts the success rate of local DRV fixing from baseline levels by 12% to 25%, reaching up to 97%. The method also produces highly diverse layout variants, covering a broad spectrum of complex violations, and outperforms existing diffusion and scripting baselines in layout diversity and rule coverage.
This work significantly advances the automation of layout verification and repair, addressing the escalating complexity of advanced nodes. By integrating deep learning with industrial validation, it paves the way for fully automated, reliable chip design workflows. Future research will focus on expanding model generalization, reducing data requirements, and incorporating multi-modal inputs to further enhance spatial understanding and repair capabilities, ultimately transforming semiconductor manufacturing into a more efficient, intelligent process.
Deep Analysis
Background
随着半导体工艺不断缩小到sub-2nm，设计规则的复杂性急剧增加。传统的DRC检测和修复方法依赖硬编码规则模板和手工调试，难以应对条件多变、层次繁复的几何关系。近年来，深度学习技术，尤其是Transformer和视觉-语言模型（VLM），在EDA中的应用逐步展开，但多层几何关系的空间推理仍是难点。工业界对自动化、智能化局部违规修复的需求日益增长，亟需结合深度学习与工业验证工具的创新方案，以应对复杂环境中的规则理解和几何推理挑战。
Core Problem
核心问题在于：如何在复杂多层布局环境中，自动识别并修复设计规则违规，特别是那些依赖多层几何关系和条件规则的违规行为。现有方法多依赖硬编码模板或单层图像处理，难以捕捉多层几何关系和条件规则的细节，导致修复效果有限，且难以推广到新工艺节点。解决这一问题需要具备空间推理、规则理解和多层几何建模能力的智能系统，能在复杂环境中实现高效、可靠的违规检测与修复。
Innovation
本研究的创新点包括：1）提出基于自监督的多层布局几何序列化方法，将复杂几何信息转化为结构化文本，支持深度模型学习空间关系；2）引入自然语言条件采样机制，生成潜在违规布局，增强多样性和规则覆盖；3）微调规则感知的VLM，实现对复杂条件规则的理解和根因分析；4）结合工业DRC验证，自动生成违规-修复对，提升局部修复的自动化水平。这些创新突破了传统模板和单层图像处理的局限，提供了端到端的深度学习解决方案，显著提升了在复杂、多条件环境中的违规检测和修复能力。
Methodology
- ��多层几何序列化：将布局切片，提取连接组件，转化为结构化文本，编码边界、多边形和层信息。•自监督训练：利用掩码预测机制，训练模型在无标签条件下重建掩码多边形，增强几何理解。•自然语言引导采样：在推理中加入规则描述，利用高温采样生成多样违规布局，确保多样性。•工业DRC验证：对生成布局进行规则验证，标注违规位置，形成训练样本。•微调VLM：结合违规检测和描述任务，训练模型理解空间关系和规则语义。•局部修复：利用微调模型指导AI代理，结合检测工具，自动修复违规布局，确保规则合规。
Experiments
采用真实的sub-2nm布局数据，训练自监督模型和微调VLM，验证生成布局的多样性和规则覆盖。对比基线包括D3PM扩散模型和脚本生成方法。指标涵盖布局熵、唯一拓扑、违规触发规则数。实验中，模型在100个实际案例中修复成功率最高达97%，显著优于传统方法。通过消融分析验证自然语言引导和多层序列化的有效性，展示模型在复杂条件和多层交互中的优势。
Results
模型在违规检测和修复任务中表现优异，F1值达61.6%，比Gemini-3-Pro高出20%以上。布局多样性方面，Entropy值达5.07，生成289个唯一拓扑，触发29类VIA和34类金属规则。修复成功率在复杂违规场景中提升12%至25%，最高达97%。这些数据验证了模型在复杂几何和条件规则环境中的强大能力，展示了深度学习在工业级芯片设计中的应用潜力。
Applications
该方法可直接应用于芯片设计流程中的局部布局修复环节，提升自动化水平，减少人工干预。适用于先进工艺节点的复杂布局环境，帮助设计工程师快速定位和修复违规区域，确保设计符合工艺规则。长远来看，结合自动化布局生成、规则理解和修复，将推动芯片设计向全自动化、智能化迈进，降低成本，提高效率。
Limitations & Outlook
模型在极端复杂布局中仍可能出现偏差，尤其在几何重叠或模糊规则边界时表现不佳。训练依赖大量真实布局和工业验证，数据采集成本高。推理中的高温采样虽增加多样性，但可能引入低质量或无关布局，需优化采样策略。未来需增强模型泛化能力，减少对大量标注数据的依赖，提升鲁棒性。
Abstract
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, dense multi-layer routing geometries, and foundry-specific constraints. While Large Language Models (LLMs) have recently demonstrated strong capabilities in EDA scripting and documentation, their application to visual layout understanding remains largely unexplored: diagnosing DRC violations from layout imagery demands precise geometric reasoning and foundry-specific rule knowledge absent from general-purpose VLM training. We propose SCALE, a framework with a self-supervised layout-generation stage for local DRV fixing at advanced nodes. Multi-layer layout geometry is serialized into structured text, and a fine-tuned language model learns to reconstruct randomly masked polygons from surrounding BEOL context alone without violation labels. At inference, natural-language rule constraints and high-temperature sampling steer generation toward diverse, violation-prone layout variants validated by an industrial signoff DRC checker, producing DRC-annotated layout--violation pairs used to fine-tune a domain-adapted DRC-VLM. This VLM provides rule-aware geometric guidance for local DRV repair, boosting state-of-the-art agents' solve rates by +12--25% (up to 97%) on 100 real sub-2nm cases spanning enclosure, spacing, width, and color-spacing violations.