Spicing up Genetic Netlist Generation with LLMs

Analog circuit design has evolved from manual, experience-based methods to automated optimization techniques like Bayesian optimization, reinforcement learning, and deep learning. Early works such as Bayesian Optimization for transistor sizing and RL-based power converter design have shown promise. However, topology synthesis remains difficult due to the discrete nature of device interconnections and the nonlinear impact on circuit behavior. Recent efforts incorporate graph neural networks and generative models, but these often focus on specific circuit families like operational amplifiers or filters. The advent of LLMs offers new opportunities for structured text generation, yet their integration into topology search remains underexplored. The challenge is to combine the strengths of deep learning with physical simulation to explore vast, complex design spaces efficiently.

The core challenge is efficiently exploring the enormous, discrete topology space of transistor-level circuits to find high-performance solutions. Existing genetic algorithms require many evaluations, leading to high computational costs, and tend to converge prematurely. Simply generating circuits with LLMs lacks reliability due to the risk of reproducing canonical solutions or producing invalid designs. The key bottleneck is balancing exploration and exploitation while ensuring physical validity and robustness across process variations. Developing a method that can guide the search intelligently, incorporate domain knowledge, and validate designs via simulation is critical for advancing automated analog circuit synthesis.

This work introduces three main innovations: 1) embedding LLMs as proposal operators within a genetic search, enabling structured, informed candidate generation; 2) proposing IGEL, which prompts high-quality circuits to generate new topologies based on inspiration, leveraging LLMs’ code generation strength; 3) integrating SPICE simulation for performance validation, ensuring physical realism. Unlike prior methods that rely solely on pure optimization or unstructured generation, this approach combines deep generative modeling with physical evaluation, significantly improving search efficiency and solution quality. It opens new avenues for hybrid AI-driven design automation, capable of discovering unconventional, high-performance topologies.

• �� Initialize a population of candidate circuits using traditional genetic operators. • Select top-performing circuits from the current elite set for inspiration. • Construct prompts combining multiple high-quality circuits, formatted with reasoning or diff-based edits. • Pass prompts to the LLM (e.g., Qwen3.5 27B), which analyzes and generates new netlists. • Preprocess generated netlists by removing duplicates and simplifying transistor representations. • Evaluate each candidate with Ngspice across 17 corners, calculating rewards based on accuracy and voltage separation. • Update the elite set with top solutions, applying crossover, mutation, pruning, and IGEL operators. • Repeat for 131,072 steps, iteratively improving circuit performance.

The experiments focus on synthesizing transistor-level circuits for Iris classification, using SkyWater PDK components. The dataset is split into training, validation, and test sets, with 150 samples total. Performance metrics include classification accuracy and output voltage separation, evaluated under multiple process, voltage, and temperature corners. Baseline comparisons include non-guided genetic algorithms and GNN-based methods. Hyperparameters such as proposal steps, model size, and prompt design are tuned. The effectiveness of IGEL is assessed through ablation studies, analyzing prompt formats, reasoning, and model size effects. Results demonstrate that LLM guidance accelerates convergence and yields higher-quality circuits.

The median reward increased from 0.747 to 0.810 with IGEL, with the best circuit reaching 0.855. Test accuracy on the Iris task reached 93.3%, outperforming baselines. Ablation results show reasoning-enabled prompts and structured edits outperform other configurations. Larger models (e.g., Qwen3.5 27B) produce better proposals, confirming the benefit of scale. The approach maintains robustness across multiple corners, validating its practical utility in real-world scenarios.

This framework can be applied to automate the design of high-performance analog circuits, such as sensors, amplifiers, and signal processors, reducing manual effort and design cycle. It is particularly suited for tasks requiring unconventional topologies or multi-objective optimization, where traditional methods struggle. The approach can also facilitate rapid prototyping and exploration in research settings, accelerating innovation in analog IC design.

High computational cost due to large LLM inference and extensive SPICE simulations limits scalability. Model bias and simulation inaccuracies may affect solution quality. Current focus on specific tasks like Iris classification may restrict generalization. Future work needs to optimize prompt strategies, incorporate hardware validation, and extend to broader circuit classes and multi-objective scenarios.