Aicir: A Full-Stack Quantum Circuit Simulator with AscendNPU Support

Key Findings

Methodology

Aicir employs a layered architecture integrating paired real tensors, fixed-rank gate views, and hardware-specific formulas to enable native execution on Ascend NPU. Its core includes modules for circuit construction, multiple state representations (state vector, density matrix, tensor network, MPS), measurement, differentiation, and variational algorithms. By encapsulating 19 interface methods, it connects the numerical layer with simulation engines and supports cross-device partitioning and reverse-mode autograd. Validation involved disabling CPU fallback, testing communication and gradients across 2, 4, and 8 NPUs, confirming path correctness and scalability.

Key Results

On layered circuits (GHZ, QFT, random), CPU runtime of Aicir matches Qiskit Aer (within 0.97-1.28×) and Cirq (within 0.76-1.10×). Native NPU execution verified path correctness without speedup focus. Distributed simulation across multiple NPUs maintained gradient accuracy and communication integrity.
Support for noise simulation, tensor network, and MPS engines broadens application scope. Performance tests demonstrate effective scalability and correctness in multi-NPU environments.
The platform enables advanced variational algorithms, quantum machine learning, and architecture search, offering a flexible, hardware-aware simulation environment that bridges classical and quantum computing.

Significance

This work addresses the critical bottleneck of hardware-specific quantum simulation, especially on NPUs, by providing a native, scalable, and versatile platform. It enhances the ability to test large-scale, noise-aware quantum algorithms, accelerates research in quantum machine learning and architecture optimization, and paves the way for hardware-aware quantum software development. The integration of multiple state representations and distributed strategies marks a significant step toward practical quantum simulation on diverse hardware platforms, fostering broader adoption and innovation.

Technical Contribution

Aicir introduces a novel simulation path based on paired real tensors and hardware-specific formulas, enabling native execution on Ascend NPUs. Its comprehensive API encapsulates circuit construction, state evolution, measurement, and differentiation, supporting multiple state representations and distributed simulation. The platform's architecture allows seamless switching between CPU, GPU, and NPU backends, with a focus on path correctness and scalability. Its integration of architecture search methods and multi-device partitioning distinguishes it from GPU-centric simulators, offering new possibilities for hardware-aware quantum algorithm development.

Novelty

This is the first full-stack quantum circuit simulator with native support for Huawei Ascend NPUs, leveraging hardware-specific paths and multi-device partitioning. Unlike existing GPU-focused tools, Aicir exploits NPU capabilities for efficient, scalable simulation, integrating noise, differentiation, and architecture search within a unified framework. Its innovative use of paired real tensors and fixed-rank gate views enables path correctness verification without relying on complex arithmetic, representing a significant advancement in hardware-specific quantum simulation.

Limitations

Currently optimized for circuit-level simulation, it does not extend to electronic structure calculations or other quantum chemistry applications. Performance may vary with circuit complexity and size, especially in large distributed setups.
Hardware-specific paths depend on Ascend NPU features, limiting portability and requiring further optimization for other hardware. Complex circuits may still face scalability challenges due to communication overhead.
Support for noise models is limited; future work should incorporate more comprehensive error and decoherence simulations to better reflect real hardware conditions.

Future Work

Future directions include expanding support for more complex quantum algorithms, optimizing distributed communication protocols, and integrating error mitigation strategies. Enhancing scalability for larger circuits and broader hardware compatibility will be prioritized. Additionally, coupling with quantum hardware for hybrid simulation and real-time validation is envisioned to accelerate quantum software development.

AI Executive Summary

Quantum computing offers transformative potential for solving problems beyond classical capabilities, but current hardware limitations—such as noise, scale, and fidelity—pose significant challenges. To address these, quantum circuit simulators serve as vital tools, enabling researchers to design, test, and validate algorithms on classical platforms before deploying on quantum hardware. Traditionally, high-performance simulators rely heavily on GPU acceleration, yet support for other accelerators like NPUs remains scarce. This gap restricts the diversity of computing platforms available for quantum research.

In response, this paper introduces Aicir, a full-stack quantum circuit simulator optimized for Huawei's Ascend NPU. Its core innovation lies in leveraging hardware-specific paths—paired real tensors, fixed-rank gate views, and tailored formulas—to enable native execution directly on the NPU, avoiding costly memory passes and ensuring path correctness. The architecture supports multiple state representations, noise simulation, tensor network engines, and distributed simulation across multiple NPUs, making it highly versatile.

Experimental validation demonstrates that Aicir achieves CPU performance comparable to established simulators like Qiskit Aer and Cirq. More importantly, native NPU execution confirms path correctness and scalability, with successful distributed simulations across 2, 4, and 8 NPUs. These results showcase the platform's ability to handle large, complex circuits while maintaining accurate gradients and communication integrity.

Beyond performance, Aicir supports a broad range of applications, including variational quantum algorithms, quantum machine learning, and architecture search, addressing key needs in quantum algorithm development. Its hardware-aware design paves the way for future integration with quantum hardware and multi-platform simulation, promising to accelerate the evolution of quantum software ecosystems. Although currently focused on circuit-level simulation, ongoing work aims to extend capabilities to more complex applications, ultimately fostering a more flexible, scalable, and hardware-efficient quantum simulation landscape.

Deep Dive

Glossary

Paired Real Tensors (配对实数张量)

一种将复数拆分为实部和虚部的张量表示，便于在硬件上高效运算。In this paper, used to implement path-specific operations on Ascend NPU.

用于实现硬件路径，避免复杂的复数运算。

Fixed-Rank Gate Views (固定秩门视图)

一种将量子门表示为固定秩张量的技术，优化硬件路径中的存储和计算。应用于NPU路径优化。

确保在硬件上高效执行门操作。

Reverse-Mode Autograd (反向传播自动微分)

一种自动微分技术，通过反向传播计算梯度，支持微分路径在多设备间的完整性。

支持变分算法和梯度优化。

Tensor Network (张量网络)

一种利用张量连接结构高效表示多体量子态的方法，适用于低秩或局部纠缠电路。

用于张量网络引擎，提升模拟效率。

Matrix Product State (矩阵乘积态)

一种特殊的张量网络表示，适合低纠缠状态的高效模拟。支持在多NPU环境下的分布式模拟。

实现大规模分布式量子态模拟。

Open Questions Unanswered questions from this research

1 如何进一步优化硬件路径以支持更复杂电路和误差模型，仍是未来研究重点。现有路径对大规模电路的扩展性有限，需探索更高效的通信与存储策略。
2 多平台支持（如GPU、FPGA）与NPU的集成方案尚未成熟，未来需实现跨硬件的无缝迁移与优化。

Abstract

Quantum computing is a promising way to study problems that are difficult for classical methods, but current quantum hardware still faces limits in scale, noise, and fidelity. Running quantum algorithms on physical machines can also be costly. Quantum circuit simulators therefore remain important because they let researchers design and test algorithms on classical computers before using quantum hardware. Most high-performance simulators provide GPU backends, while few offer native support for NPUs. This gap limits the computing platforms available for quantum-algorithm research. We developed Aicir to provide a full-stack quantum circuit simulator with a native Huawei Ascend NPU backend. Aicir connects circuit construction, several state representations, measurement, differentiation, variational algorithms, quantum machine learning, and quantum architecture search through one programming model. It also supports noise simulation, tensor-network and matrix-product-state engines, and distributed state simulation. On the NPU, paired real tensors, fixed-rank gate views, and hardware-specific formulas keep the tested simulation paths on the device. The same representation lets Aicir partition a state across $2^{p}$ NPUs while retaining reverse-mode differentiation. We validated native execution with CPU fallback disabled and checked distributed communication and gradients on 2, 4, and 8 NPUs. For the tested fused layered circuits, Aicir's CPU runtime is within $0.97$--$1.28\times$ that of Qiskit Aer and $0.76$--$1.10\times$ that of Cirq. These results place its CPU execution in the same range as established simulators for this workload, while the NPU tests establish correct native execution rather than CPU-to-NPU speedup.

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