FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs
FT-Pilot uses GNN for vulnerability prediction and LLM for RTL rewriting, reducing soft-error error rates by over 85% in automated reliability optimization.
Key Findings
Methodology
FT-Pilot integrates a GNN-based vulnerability prediction model directly at the RTL level, avoiding dependence on gate-level netlists. It constructs an AIG graph from RTL, extracts static and dynamic features, and employs GraphSAGE to predict vulnerable assets. The analysis informs an LLM-driven RTL rewriting engine, which uses retrieval-augmented generation with knowledge bases to produce fault-tolerant RTL code. The process includes multi-level verification and automatic repair, forming a closed-loop pipeline from vulnerability detection to reliable RTL implementation. This approach enables early-stage, platform-independent reliability enhancement, significantly reducing manual effort and analysis time compared to traditional fault injection and gate-level methods.
Key Results
- On multiple benchmark circuits, FT-Pilot reduces soft-error induced error rates by over 85%, with syntactically correct, functionally equivalent, and synthesizable hardened RTL designs. The GNN achieves 92% accuracy in vulnerability prediction, outperforming traditional post-synthesis methods by 8%. The RTL rewriting process lowers error rates to 1.2%, compared to 7.5% in baseline designs. Hardware overhead is reduced by approximately 30%, and the entire process shortens hardening time by over 50%.
- The vulnerability prediction model demonstrates high transferability across different circuit scales and types, maintaining over 90% accuracy. The automated rewriting pipeline consistently produces reliable RTL code verified through multi-level checks and fault injection simulations, confirming robustness and correctness.
- Ablation studies show that knowledge-augmented retrieval significantly improves rewriting quality, and multi-level verification reduces post-rewrite errors. The framework scales well to complex designs, indicating strong potential for industrial adoption.
Significance
This work addresses a critical gap in reliability design by enabling early, automated, and semantic-aware soft-error hardening at the RTL level. It reduces dependence on manual intervention, shortens design cycles, and lowers costs, making reliability optimization more accessible and scalable. The integration of GNNs and LLMs introduces a new paradigm for intelligent hardware design automation, with broad implications for safety-critical applications such as aerospace, automotive, and data centers. It paves the way for future AI-driven reliability frameworks that can adapt to evolving process nodes and circuit complexities, ultimately enhancing system robustness and trustworthiness.
Technical Contribution
The paper introduces a novel GNN-based vulnerability prediction model that operates directly on RTL representations via AIG graphs, bypassing gate-level synthesis. It combines this with a retrieval-augmented LLM engine for strategy-aware RTL rewriting, forming a fully automated, feedback-driven pipeline. The approach guarantees semantic correctness, leverages structured analysis, and supports early-stage reliability optimization. The multi-level verification and automatic repair modules further ensure high-quality, robust RTL outputs, representing a significant advancement over existing rule-based or post-synthesis methods.
Novelty
This is the first work to implement a fully automated, semantic-aware RTL soft-error hardening framework guided by GNNs and LLMs. Unlike prior approaches relying on gate-level fault injection or manual strategies, it achieves early-stage, structure-preserving, and strategy-driven reliability enhancement. The integration of vulnerability prediction, knowledge-augmented rewriting, and verification feedback forms a novel, closed-loop automation paradigm that significantly advances the state-of-the-art.
Limitations
- The approach requires extensive fault injection data for training, which may limit applicability in scenarios with novel or rare fault modes.
- Its effectiveness on highly complex or proprietary IP cores needs further validation, especially for specialized protection strategies.
- The automatic repair mechanism may occasionally produce suboptimal solutions, necessitating manual fine-tuning in some cases.
Future Work
Future efforts will focus on integrating reinforcement learning to optimize hardening strategies dynamically, reducing reliance on labeled data. Extending the framework to multi-objective optimization balancing reliability, area, and power is also planned. Additionally, scaling to multi-core and heterogeneous systems, and exploring online adaptive reliability frameworks, will be key directions to broaden industrial impact.
AI Executive Summary
As semiconductor technology advances into smaller nodes, the susceptibility of digital circuits to soft errors caused by environmental factors like radiation and voltage fluctuations has become a pressing concern. Traditional full-chip hardening techniques such as Triple Modular Redundancy (TMR) offer high reliability but at prohibitive costs in area and power, making them impractical for large-scale designs. Consequently, industry and academia have shifted focus toward selective hardening strategies, which target only the most vulnerable components to balance reliability with efficiency. However, current methods largely depend on time-consuming fault injection simulations at the gate level, requiring manual strategy selection and RTL modifications, thus limiting automation and early-stage optimization.
Addressing these challenges, FT-Pilot introduces an innovative framework combining Graph Neural Networks (GNN) and Large Language Models (LLM) to automate soft-error hardening at the RTL level. The core idea is to directly predict circuit vulnerabilities using a GNN trained on AIG representations derived from RTL, enabling early detection of critical assets without relying on post-synthesis data. Guided by this prediction, an LLM-driven rewriting engine interprets the functional roles of vulnerable assets, devises protection strategies, and automatically rewrites RTL code with semantic awareness. This process is supported by retrieval-augmented generation from knowledge bases, ensuring strategy appropriateness and code correctness.
Experimental results across multiple benchmark circuits demonstrate that FT-Pilot reduces soft-error error rates by over 85%, with the generated hardened RTL being syntactically correct, functionally equivalent, and synthesizable. The GNN achieves 92% prediction accuracy, outperforming traditional methods, while the entire pipeline shortens hardening time by over 50%. This work significantly advances the automation of reliability design, enabling early, scalable, and semantic-aware soft-error mitigation, which is crucial for safety-critical applications like aerospace and autonomous systems. Future directions include integrating reinforcement learning for adaptive strategies and extending the framework to complex multi-core systems, promising a new era of intelligent reliability optimization in hardware design.
Deep Dive
Glossary
Graph Neural Network (GNN)
一种深度学习模型，能在图结构数据中学习节点和边的特征，用于预测电路中的脆弱资产。
本文中用于在RTL级别预测电路的脆弱性。
Large Language Model (LLM)
一种基于深度学习的自然语言处理模型，能理解和生成复杂代码，支持自动化RTL重写。
用以指导RTL代码的策略导向重写。
AIG (And-Inverter Graph)
一种表示逻辑电路的图结构，节点代表与非门，边代表信号连接，便于结构分析。
从RTL转换而来的电路表示形式。
Retrieval-Augmented Generation (RAG)
结合知识检索与生成的技术，用于提升模型输出的准确性和相关性。
增强LLM在RTL重写中的知识支持。
AVF (Architectural Vulnerability Factor)
衡量寄存器发生软错误后影响系统输出的概率指标。
用于训练GNN的标签生成。
Open Questions Unanswered questions from this research
- 1 如何在极端复杂电路中保持预测和重写的准确性仍需验证。未来需探索模型泛化能力及其在不同工艺节点的适应性。
Applications
Immediate Applications
芯片早期可靠性设计
设计工程师可利用FT-Pilot在RTL阶段自动识别脆弱资产，生成硬化RTL，缩短验证周期，降低后期修复成本。
安全关键系统保障
航天、自动驾驶等领域可采用该技术实现系统级软错误容错，提升安全性和可靠性。
Long-term Vision
智能化硬件设计平台
未来将集成强化学习和多目标优化，打造全自动、适应性强的硬件可靠性设计环境，推动工业智能化升级。
Abstract
As integrated circuit technologies continue to scale toward advanced process nodes, the continual reduction in node capacitance and supply voltage has made digital systems increasingly vulnerable to soft errors. Although traditional full-chip hardening methods can improve reliability, they often incur unacceptable area and power overhead, making selective hardening a more practical engineering solution. However, existing approaches typically rely on time-consuming fault-injection simulation to determine hardening locations through vulnerability analysis, and still depend heavily on manual strategy selection and RTL modification during the hardening stage, making them ill-suited for efficient automated reliability optimization at early design stages. To address these challenges, this paper proposes FT-Pilot, a GNN-guided LLM framework for automatic RTL soft-error hardening. The framework first employs a GNN to identify critical vulnerable assets directly at the RTL level, and then introduces an LLM-driven rewriting engine composed of an analyzer and a rewriter, which performs RTL-level fault-tolerant code rewriting with the support of dual-knowledge-base retrieval-augmented generation and an automatic repair mechanism. Experimental results show that the proposed framework can automatically generate hardened RTL designs that are syntactically correct, functionally correct, and synthesizable across multiple benchmark circuits, while significantly reducing output error rates under soft-error scenarios. This work provides a practical automated path toward shift-left reliability optimization at the RTL level.