Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing
Introduces PostEDA-Bench with 145 tasks to evaluate LLMs in DRC fixing and PPA optimization.
Key Findings
Methodology
PostEDA-Bench is a hierarchical benchmark comprising DRC-Essential, DRC-Reasoning, PPA-Mono, and PPA-Multi tasks, evaluated using open-source (OPENROAD) and commercial (DC+INNOVUS) toolchains. Multiple models (ReAct, Proposer-Critic, ORFS-Agent) and multi-modal inputs (including layout images) are tested. Metrics include success rate (SR), violation reduction rate (VRR), and normalized improvement score (NIS), providing comprehensive performance assessment across synthetic and real-world scenarios.
Key Results
- Models perform well on synthetic DRC-Essential (up to 85.50%) and single-objective PPA-Mono (up to 64.56%), but success rates drop sharply on practical residual violations (36.66%) and multi-objective trade-offs (20%).
- Visual augmentation consistently improves DRC task performance by 10-15%, highlighting the benefit of multi-modal inputs. In multi-objective PPA tasks, models struggle with balancing constraints, often producing negative NIS scores, indicating constraint regression.
- Geometric reasoning and multi-constraint trade-offs remain key bottlenecks, with models showing limited ability to handle interacting violations and complex Pareto front navigation in real-world designs.
Significance
This work addresses a critical gap in evaluating AI-driven post-EDA automation, providing a systematic, multi-level benchmark that closely mirrors industrial design challenges. It offers insights into the current capabilities and limitations of LLMs in complex geometric reasoning and multi-objective optimization, guiding future research toward more robust, generalizable solutions. The benchmark supports the development of intelligent tools that can significantly reduce manual effort, accelerate chip turnaround, and lower costs, ultimately advancing the automation frontier in chip design.
Technical Contribution
The paper introduces a layered benchmark framework combining diverse tasks—rule understanding, geometric reasoning, and Pareto optimization—evaluated with multi-modal inputs and multiple model architectures. It establishes a machine-checkable evaluation pipeline, enabling reproducible, objective performance measurement. The integration of synthetic and real design data, along with multi-level difficulty settings, provides a comprehensive platform for advancing AI in post-EDA tasks, setting a new standard for systematic assessment.
Novelty
This is the first comprehensive benchmark to evaluate LLMs on both DRC fixing and multi-objective PPA optimization within a hierarchical, multi-modal framework. Unlike prior work limited to script generation or single-task evaluation, PostEDA-Bench captures the complexity of real chip design scenarios, emphasizing geometric reasoning and constraint trade-offs, thus representing a significant innovation in automated design assessment.
Limitations
- Models still struggle with complex geometric reasoning and multi-constraint trade-offs, especially in interacting violation chains, indicating the need for better spatial understanding and planning capabilities.
- Evaluation relies on specific toolchains (OPENROAD, DC+INNOVUS), and generalization to other environments remains untested, potentially limiting industrial applicability.
- Current methods primarily focus on post-flow repair and tuning, with less emphasis on integrating front-end design automation, which is essential for full-chip automation.
Future Work
Future directions include enhancing multi-modal learning with 3D layouts and process data, integrating reinforcement learning for better trade-off management, and expanding the benchmark with real industrial case studies. Developing models with stronger geometric reasoning and constraint handling will be key to achieving fully autonomous chip design workflows.
AI Executive Summary
The last stage of chip design, often called the 'tail-end' optimization, involves fixing residual design rule violations (DRC) and meeting power, performance, and area (PPA) targets. While traditional EDA tools like Cadence Innovus and Synopsys Design Compiler are efficient, they struggle with complex layouts and multi-objective trade-offs, often requiring manual intervention. To address this, the authors introduce PostEDA-Bench, a hierarchical benchmark with 145 tasks that simulate real-world post-EDA challenges.
This benchmark covers a spectrum of tasks—from simple rule understanding to complex geometric reasoning and multi-objective Pareto optimization—reflecting the actual difficulties faced in industrial chip design. It evaluates multiple large language models (LLMs) with multi-modal inputs, including layout images, across different toolchains. The results reveal that while models excel in synthetic, simplified tasks, their performance drops significantly in practical scenarios, especially in geometric reasoning and constraint balancing.
Importantly, visual inputs improve DRC repair success, indicating that multi-modal data helps models understand spatial relationships better. However, models still face major hurdles in multi-objective trade-offs, often failing to balance competing PPA metrics effectively. This highlights the need for further research into geometric reasoning and multi-constraint optimization within AI models.
Overall, PostEDA-Bench provides a comprehensive, realistic platform for evaluating AI's potential in automating the complex, multi-faceted tasks of modern chip design. It paves the way for future breakthroughs in intelligent, fully automated chip development, promising to reduce costs, shorten development cycles, and enable more innovative designs. Despite current limitations, this work marks a significant step toward smarter, more autonomous electronic design automation.
Deep Analysis
Background
芯片设计经历从RTL编码到版图布局的多个阶段，自动化工具如Cadence Innovus、Synopsys Design Compiler极大提升了效率。早期研究集中在逻辑合成、布局优化，代表工作如OpenROAD、RePlAce等。随着工艺复杂度增加，设计规则检查（DRC）成为确保制造可行性的关键环节。残余违规和多目标PPA调优依赖大量调参，效率低下。近年来，LLM在代码生成和推理中展现潜力，逐步被引入EDA后端任务，推动自动化智能化，但缺乏系统评估平台。
Core Problem
后端设计自动化面临两大难题：一是残余DRC违规的自动修复，涉及复杂几何关系和多层规则理解；二是多目标PPA优化中的折中策略难以自动实现，模型难以平衡性能、功耗和面积。这些问题限制了自动化的普及和效率提升，特别在复杂布局和工艺节点下，传统算法难以应对多维约束交互。
Innovation
提出层级化的PostEDA-Bench，创新点包括：1）多层任务设计，涵盖合成布局、实际布局、几何推理和多目标折中，模拟真实场景；2）引入多模态输入（布局图像），增强几何理解；3）结合多模型架构（ReAct、Proposer-Critic、ORFS-Agent），提升探索能力；4）机器可检验的自动评价体系，确保客观评估。这些突破了单一任务、工具链的限制，为后端自动化提供全面技术支撑。
Methodology
- �� 构建层级任务体系：包括DRC-Essential、DRC-Reasoning、PPA-Mono和PPA-Multi，分别测试规则理解、几何推理、单目标和多目标优化能力。
- �� 数据采集：从公开RTL源（RTLLM、VERILOGEVAL-Human、OPENCORES）筛选设计，映射到ASAP7工艺库，确保符合规模和可审计标准。
- �� 任务设计：利用合成布局、实际布局、违规注入和多目标折中策略，生成多样化测试案例。
- �� 模型评估：采用多模态输入（布局图像、文本提示），结合ReAct、Proposer-Critic、ORFS-Agent等架构，在开源和商业工具链上进行多轮测试。
- �� 评价指标：成功率（SR）、违规减免率（VRR）、归一化改进分（NIS）等，确保全面衡量模型性能。
Experiments
实验在OpenROAD和DC+INNOVUS工具链上进行，涵盖145个任务，分为DRC修复和PPA调优两大类。模型包括GPT-5、Gemini-3-Flash、DeepSeek-V3.2等多种架构。每个任务重复5次，采用温度0的生成策略，统计成功率和VRR。还进行了多模态输入的对比实验，验证视觉增强的效果。通过不同难度层次（L1-L3）分析模型在规则理解、几何推理和交互修复中的表现差异。
Results
模型在合成布局和单目标任务中表现优异，成功率最高达85.50%（DRC-Essential）和64.56%（PPA-Mono）；但在实际布局残余违规（DRC-Reasoning）和多目标折中（PPA-Multi）中，成功率下降至36.66%和20%。引入视觉输入后，DRC任务成功率提升10-15%，验证了多模态输入的有效性。多目标任务中，模型在平衡指标方面表现出明显瓶颈，出现负的NIS值，反映出模型在几何推理和约束折中中的不足。
Applications
该平台可用于芯片设计公司评估自动化工具的智能水平，提升DRC修复和PPA调优的效率。未来可结合全流程设计优化，推动自动化设计向更高层次智能化发展，缩短芯片开发周期，降低成本。对于研究机构，该基准提供了系统化的评估工具，推动AI在EDA中的深度应用。
Limitations & Outlook
模型在几何推理和多目标折中方面仍存在明显不足，尤其在复杂布局和交互修复链中成功率偏低。评估依赖特定工具链，泛化能力有限。未来需增强模型的几何理解和多目标策略，降低对硬件资源的依赖，提升实际工业应用的适应性。
Plain Language Accessible to non-experts
想象你在厨房做菜，厨房里有很多不同的任务：准备食材、调味、烹饪、摆盘。每一步都需要按照一定规则操作，否则菜就做不好。现在，假设你有一个聪明的机器人助手，它可以帮你检查每一步是否符合规则，还能帮你调整调料的用量，确保菜的味道、色泽和份量都达标。
这个机器人就像论文中的模型，它要在复杂的厨房环境中，理解各种规则（DRC）和目标（PPA），比如菜要不太咸、不太淡、色泽鲜亮。它需要不断学习和调整，才能帮你做出完美的菜。论文提出了一个测试平台，让我们可以评估这个机器人在不同任务中的表现，从简单的规则修复到复杂的多目标平衡。就像厨房里，机器人要学会在保持菜的味道的同时，还能控制成本和时间。这项工作让我们离让厨房自动化更进一步，未来厨房可能会由智能机器人全权管理，帮我们做出更好吃、更健康的菜。
ELI14 Explained like you're 14
想象你在学校的美术课上画画，你需要按照老师的要求画出漂亮的画，但有时候会出现一些错误，比如颜色不对或者线条不够漂亮。你有一个聪明的朋友，他可以帮你检查画作，指出哪里画得不对，还能帮你修正。这个朋友就像论文里的模型，它要在复杂的芯片设计中，检查布局是否符合规则，还要帮忙调整参数，让芯片既快又省电。
这个模型在测试平台上接受各种任务，比如修复布局中的违规，或者在性能和功耗之间找到最佳平衡。它就像你的朋友一样，学习了很多规则和技巧，试图帮你画出最完美的画。虽然它在简单任务上表现不错，但在复杂的设计中还会遇到困难，比如要同时考虑多个目标，做出折中。这个研究让我们知道，未来的芯片设计可能会由这些聪明的模型帮忙，大大提高效率，减少错误。
Abstract
LLM-based agents are increasingly applied to the "last mile" of Electronic Design Automation (EDA): repairing residual sign-off Design Rule Check (DRC) violations and converging Power-Performance-Area (PPA) targets after tool runs. Existing EDA-LLM benchmarks, however, omit DRC fixing entirely and rely on flat hierarchies tied to a single toolchain. We introduce PostEDA-Bench, a hierarchical benchmark with 145 tasks across DRC-Essential, DRC-Reasoning, PPA-Mono, and PPA-Multi, supported by EDA toolchains with machine-checkable evaluation. Across eight commercial and open-source LLMs under multiple agent scaffolds, we find that agents handle synthetic DRC-Essential and single-objective PPA-Mono reasonably well but degrade sharply on the more practical DRC-Reasoning, where the best success rate is 36.66%, and PPA-Multi, where the best success rate is 20.00%; vision augmentation consistently enhances DRC-Bench; and trade-off reasoning, rather than knob knowledge, is the dominant PPA-Multi bottleneck.