Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors

As integrated circuit technology advances, process variations such as intra-die mismatches, doping fluctuations, and threshold voltage shifts become critical design factors. For modern designs with highly replicated structures like SRAM cell arrays, yield analysis is essential. The ultimate challenge is Yield Multi-Corner Analysis (YMCA), where circuits must be validated across more than 25 Process-Voltage-Temperature (PVT) corners. This creates a combinatorial cost barrier: naive Monte Carlo simulation requires thousands of evaluations per corner to achieve acceptable accuracy. For a 32-transistor SRAM across 25 corners, this translates to over 25,000 SPICE simulations requiring weeks of computation, making iterative design impractical.

The field's pursuit of acceleration has followed two main paths, both reaching fundamental barriers. Importance Sampling (IS) methods like MNIS achieved remarkable 100× speedups through automated norm-minimization, becoming an industry standard. However, simple Gaussian priors create a model capacity barrier: single-point assumptions cannot capture complex, nonlinear failure regions. Subsequent clustering approaches remained limited by their underlying strong model assumptions.

The second path pursued expressive surrogate-based acceleration. Methods based on Gaussian Processes, deep kernels, and normalizing flows successfully broke the model capacity barrier by learning complex, nonlinear failure boundaries. However, this power comes at a steep cost: careful hyperparameter tuning, including kernel selection and network architecture search. The state-of-the-art performance, to some extent, is achieved by careful tuning for particular benchmark problems and is unable to generalize. Thus, these methods are rarely implemented in industrial environments.

Yield Multi-Corner Analysis (YMCA) is a critical problem in integrated circuit design, involving the validation of circuits across multiple Process-Voltage-Temperature (PVT) corners. Traditional methods face a fundamental bottleneck: simple models achieve automation but perform poorly on nonlinear circuits, while complex AI models capture intricate behaviors but require extensive hyperparameter tuning, forming a tuning barrier. This barrier has blocked the adoption of modern AI methods in industrial yield analysis, as engineers cannot afford hours of expert tuning per design iteration only to face unpredictable performance.

The core innovation of this study lies in introducing a framework based on learned priors for circuit validation in multi-corner analysis. • For the first time, learned priors are employed in circuit validation, breaking the tuning barrier of traditional methods. • By leveraging a foundation model pre-trained on millions of regression tasks, the method achieves zero hyperparameter tuning. • The model performs in-context learning, adapting to each circuit without retraining. • Its attention mechanism automatically identifies shared circuit physics across operating conditions, enabling cross-corner knowledge transfer. • Combined with an automated feature selector (from 1152D to 48D), the method achieves state-of-the-art accuracy (mean relative errors as low as 0.11%) with zero tuning, reducing total validation cost by over 10 times.

The methodology of this study includes the following key steps: • Learned Priors: By leveraging a foundation model pre-trained on millions of regression tasks, the method achieves zero hyperparameter tuning. • In-Context Learning: The model adapts to each circuit without retraining. • Attention Mechanism: Automatically identifies shared circuit physics across operating conditions, enabling cross-corner knowledge transfer. • Automated Feature Selector: Reduces circuit features from 1152 dimensions to 48 dimensions, improving computational efficiency. • Experimental Design: Validation of circuits across multiple PVT corners to evaluate the method's accuracy and efficiency.

The experimental design includes validating circuits across multiple PVT corners to evaluate the method's accuracy and efficiency. • Datasets: Using SRAM macros in FreePDK45 (45 nm), including critical peripherals. • Baselines: Compared with Monte Carlo (MC), BI-BD and BI-BC, OPT, and others. • Evaluation Metrics: Relative error, Mean Relative Error (MRE), speedup, etc. • Hyperparameters: Zero hyperparameter tuning, automated feature selector reduces circuit features from 1152D to 48D.

Experimental results show that the method achieved a mean relative error as low as 0.11% in multi-corner analysis, comparable to state-of-the-art methods, without any hyperparameter tuning. • Validation cost was reduced by over 10 times, significantly improving computational efficiency. • The automated feature selector reduced circuit features from 1152 dimensions to 48 dimensions while maintaining high accuracy. • In cross-corner knowledge transfer, the learned prior model achieved over 70% error reduction through the attention mechanism, especially in challenging corners.

Application scenarios in integrated circuit design include: • Yield analysis of modern SRAM cell arrays: Improving design reliability and efficiency through multi-corner analysis. • Automated circuit validation processes: Reducing hyperparameter tuning time and improving validation efficiency. • Industrial yield analysis: Achieving automation without sacrificing accuracy, supporting rapid iteration design.

Despite the method's excellent performance in multi-corner analysis, it may still exhibit some errors when dealing with extremely nonlinear circuits. This is because the foundation of the learned priors still relies on the diversity of pre-trained data. Additionally, the dimensionality reduction process by the automated feature selector, while improving computational efficiency, may lose some critical detail information for specific circuit behaviors. Future research directions include expanding the training dataset of the learned priors to improve performance in extremely nonlinear circuits and validating the method's practical effectiveness in larger-scale industrial applications.