SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks

Spiking Neural Networks (SNNs) represent the third generation of neural network models, extending conventional artificial networks by incorporating temporal dynamics and event-driven computation. Unlike traditional Artificial Neural Networks (ANNs), where neurons communicate through continuous activations, SNNs transmit discrete spike events, enabling sparse and asynchronous processing. This characteristic leads to substantially lower energy consumption and improved temporal precision, which are particularly advantageous for edge and embedded systems. At the computational level, a range of neuron models has been proposed to emulate biological spiking behavior. Highly detailed models such as Hodgkin–Huxley provide strong biological realism but are computationally intensive and impractical for hardware implementation. Simplified models, most notably the Leaky Integrate-and-Fire (LIF) neuron, abstract spiking dynamics using lightweight equations that significantly reduce computational and hardware overhead. Information in SNNs is encoded as sequences of spikes using neural coding schemes that directly influence computational efficiency. Common strategies include rate coding, where firing frequency represents signal strength, and temporal codes such as time-to-first-spike (TTFS) and phase coding, which exploit precise spike timing for low-latency computation. The choice of neuron model and coding scheme strongly impacts implementation complexity, power consumption, and latency in neuromorphic hardware. In this work, the LIF model is selected due to its deterministic timing behavior and hardware simplicity, making it well suited for compact neuromorphic architectures targeting real-time embedded operation.

While large-scale SNNs aim to replicate complex cortical networks, many embedded applications operate efficiently on compact, task-specific architectures. In this context, small-scale SNNs can be defined as networks with approximately 10 to 2000 neurons. Networks of this size are commonly used in robotics, signal processing, and sensor-driven applications, where energy efficiency, deterministic behavior, and low latency are critical. Despite the availability of large-scale neuromorphic platforms such as Intel’s Loihi (131,072 neurons) and SpiNNaker (up to 1 billion neurons in multi-chip configurations), many real-world applications require significantly smaller networks, leading to substantial hardware underutilization. In robotics, Gridbot employs only 1,321 neurons for spatial navigation, while NeuroPod uses merely 22 neurons on the massive SpiNNaker platform for insect-inspired locomotion. Control applications demonstrate even more extreme mismatches: autonomous racing systems operate with 39 neurons, lane-keeping controllers require 34 neurons, and event-based PID control for quadrotors utilizes approximately 35-40 neurons. Beyond control tasks, robot localization systems typically employ 700–800 neurons, while micro-scale engine optimization operates with as few as 8 neurons. These examples show that small-scale SNNs are not simplified versions of large networks but domain-optimized architectures tailored for specific spatiotemporal tasks with predictable latency, efficient memory access, and minimal communication overhead, characteristics that would be better served by dedicated small-scale neuromorphic platforms rather than running on massively over-provisioned hardware.

The core innovations of SNAP-V lie in its architectural design, combining the openness and modularity of RISC-V to enable general-purpose processing and event-driven computation on a single platform. Specific innovations include:

1) The design and implementation of a RISC-V integrated neuromorphic SoC, optimized for inference on small-scale SNNs.

2) A neuromorphic accelerator with two progressive designs: Cerebra-S (Small) establishing a baseline for performance analysis and optimization insights, and Cerebra-H (High-performance), a clustered architecture with hierarchical NoC, refined based on Cerebra-S findings.

3) RTL-level functional validation demonstrating close agreement between software and hardware inference, with an average accuracy deviation below 3%.

4) A detailed power and energy characterization revealing memory-dominated system behavior and achieving low synaptic energy per operation.

The design and implementation methodology of SNAP-V includes the following steps:

• �� Leveraging RISC-V's open and modular ISA to achieve design flexibility and compatibility with open-source SoC frameworks.
• �� Tight integration of the neuromorphic subsystem with RISC-V cores using the Rocket Custom Coprocessor (RoCC) interface.
• �� Issuing custom SNN instructions from SpikeCore via the RoCC interface for efficient configuration, spike-data transfer, and synchronization with the accelerator's event-driven pipeline.
• �� Implementing an Accelerator Controller for instruction decoding, dual NoC management, and time synchronization between the CPU and the accelerator.
• �� Using a hardware-implemented rate coding scheme to convert sensor data into spike trains and route them to neuron clusters through the NoC.
• �� Integrating spike encoding and decoding at the hardware level to achieve tighter coupling between sensing, computation, and actuation.

The experimental design includes comparing software and hardware inference across multiple network configurations to evaluate system accuracy and energy efficiency. Experiments are conducted in 45 nm CMOS technology, measuring average synaptic energy per operation. RTL-level functional validation demonstrates close agreement between software and hardware inference. Experiments also compare the performance and energy efficiency of Cerebra-S and Cerebra-H, particularly the effectiveness of Cerebra-H's hierarchical Network-on-Chip architecture in addressing communication bottlenecks.

Experimental results show an average accuracy deviation of 2.62% between software and hardware inference across multiple network configurations, and an average synaptic energy of 1.05 pJ per synaptic operation in 45 nm CMOS technology. Cerebra-H achieves a maximum clock frequency of 96.24 MHz, a 9.46-fold improvement over Cerebra-S, significantly enhancing real-time responsiveness. The hierarchical Network-on-Chip architecture of Cerebra-H effectively addresses communication bottlenecks, enhancing system efficiency and performance.

SNAP-V is suitable for applications in robotics, edge intelligence, and low-power adaptive control. Its flexible interfacing and general-purpose computation capabilities enable efficient management of SNN workloads on a single platform, while supporting additional embedded tasks such as sensor processing, control logic, and signal encoding. SNAP-V provides a resource-efficient solution for practical deployment of small-scale SNNs, promoting the adoption of neuromorphic computing in real-world applications.

While SNAP-V performs excellently in small-scale SNN applications, its architecture may not be suitable for large-scale neural networks, especially in scenarios requiring higher computational power. Additionally, although Cerebra-S is simple in design, it suffers from communication and memory access bottlenecks, affecting overall system performance. The current implementation is primarily based on 45 nm CMOS technology, which may require re-optimization in more advanced processes. Future research directions include exploring the applicability of SNAP-V in broader application scenarios, particularly performance optimization in more advanced process technologies.