Paradigm-Based Automatic HDL Code Generation Using LLMs

The evolution of hardware design increasingly demands automation to cope with rising complexity and time constraints. Traditional HDL coding relies heavily on manual effort, which is slow and error-prone. Recent advances in deep learning, especially Large Language Models like GPT-3 and GPT-4, have demonstrated potential in code generation tasks. However, their application in HDL synthesis is hindered by hallucination—producing code that appears plausible but deviates from specifications. Prior efforts involving fine-tuning models or leveraging retrieval-based augmentation (e.g., RAG) have limitations, such as high computational costs and dependency on large datasets. This context motivates the development of a structured, paradigm-driven approach that mimics human design reasoning, aiming to improve correctness without extensive retraining or data collection.

The core challenge addressed is the hallucination problem in LLM-based HDL code generation, which leads to incorrect or non-functional code. Single-pass generation often results in errors that propagate, reducing overall reliability. Existing solutions like fine-tuning or database retrieval are resource-intensive and not always effective. The difficulty lies in guiding models to produce accurate, specification-compliant code efficiently, especially for complex or ambiguous designs. Overcoming these bottlenecks is crucial for practical adoption of AI in hardware development workflows.

The main innovation is the introduction of structured paradigm blocks that encode human design strategies into prompts, guiding LLMs through complex tasks. These blocks—COMB, SEQU, and BEHAV—decompose the design process into explicit steps, such as information extraction, format conversion, and code synthesis. The classification mechanism ensures task-specific processing, while multi-round validation filters errors and reuses high-quality intermediate results. This approach reduces hallucination without fine-tuning, leveraging task decomposition and iterative refinement. The integration of logic simplification via PyEDA further enhances correctness, making the process more reliable and scalable.

• �� Design paradigm blocks tailored for combinational, sequential, and behavioral logic, each containing prompts for information extraction, format transformation, and code generation.
• �� Classify circuit specifications into appropriate paradigms using model-generated initial code, improving task alignment.
• �� Extract explicit information such as input-output relationships, timing, and state transitions from specifications.
• �� Convert extracted data into standardized formats like truth tables, state transition tables, and component lists.
• �� Generate HDL code step-by-step, employing model prompts for each sub-task, and utilize external tools like PyEDA for logic optimization.
• �� Implement a two-phase multi-round workflow where initial code is validated via testbenches, and high-quality intermediate results are reused in subsequent rounds.
• �� Apply error handling strategies like Fail-safe and Short-cut to manage format errors and optimize resource use.

The experimental setup involves the VerilogEval dataset with 299 tasks, split into human-written and GPT-generated specifications. Models (GPT-4 and GPT-4o-mini) are prompted with structured tasks, and code correctness is evaluated via Pass@k metrics, with k=1, 5, 10. The workflow includes multiple generation rounds, classification, and validation steps. Ablation studies compare single-pass, multi-round, and paradigm-based methods. Logic expressions are simplified with PyEDA, and simulation is performed using Icarus Verilog. Results are benchmarked against baseline single-pass generation, demonstrating significant improvements in correctness and robustness across datasets.

The proposed paradigm-driven, multi-round approach achieves Pass@1 of 42.5% on VerilogEval-human, outperforming baseline by 4.7%. Pass@5 and Pass@10 reach 60.7% and 66.0%, respectively, surpassing previous methods by over 10%. On VerilogEval-machine, improvements are similar, with Pass@5 and Pass@10 increasing by more than 5%. The results confirm that structured task decomposition, classification, and iterative validation effectively mitigate hallucination, leading to higher code correctness. Ablation results show that each component—paradigm matching, information reuse, multi-round validation—contributes significantly to performance gains.

This framework is suitable for automating HDL code generation in chip design, verification, and EDA tool development. It enables rapid, reliable synthesis of specification-compliant hardware modules, reducing manual effort and errors. The approach can be integrated into existing design workflows, supporting complex circuit development with minimal human intervention. Long-term, it could facilitate fully automated chip design pipelines, accelerating innovation and reducing costs in semiconductor industries.

The method's accuracy depends on the correctness of circuit classification; misclassification can degrade performance. Multi-round validation increases computational load, limiting real-time application. The approach's effectiveness on highly complex or novel circuits needs further validation, and adaptive paradigm generation could enhance generalization. Future work should address these issues to improve robustness and scalability.