A Survey of Research in Large Language Models for Electronic Design Automation

The evolution of semiconductor technology has led to exponential increases in chip complexity, demanding more intelligent and automated design tools. Traditional EDA workflows rely heavily on rule-based algorithms and heuristics, which struggle to keep pace with modern design scales. The advent of Transformer architectures and large-scale pretraining, exemplified by models like GPT-3 and GPT-4, has revolutionized NLP and is now being adapted for hardware design. Early efforts focused on automating RTL code generation, circuit verification, and specification review, leveraging the semantic understanding capabilities of these models. As model sizes grew, their ability to process multi-modal data—text, images, graphs—became crucial for capturing the rich, multi-layered information inherent in circuit design. Recent research has demonstrated that domain-specific fine-tuning, prompt engineering, and multi-modal fusion significantly enhance model performance, enabling tasks like chip specification review, logic debugging, and accelerator co-design. These advances are supported by benchmark datasets such as ISPD, DAC, and industry collaborations, which provide standardized evaluation metrics. The integration of LLMs into EDA workflows promises to reduce design cycles, improve accuracy, and facilitate innovation, marking a new era of AI-assisted hardware development.

Despite promising progress, several core challenges hinder widespread adoption of LLMs in EDA. First, the complexity of modern circuits, involving multi-layered dependencies and multimodal data, exceeds the current capabilities of models, leading to accuracy and robustness issues. Second, the high computational cost associated with training and inference of large models limits practical deployment, especially in resource-constrained environments. Third, the lack of standardized evaluation metrics and benchmarks makes it difficult to compare different approaches objectively. Fourth, the interpretability of these models remains limited, raising concerns about trust and transparency in critical design decisions. Addressing these issues is essential for transitioning from proof-of-concept to industrial-scale applications, requiring innovations in model architecture, hardware acceleration, and evaluation protocols.

This survey introduces several key innovations: 1) a multi-modal Transformer architecture that fuses textual, graphical, and image data for comprehensive circuit understanding; 2) a prompt engineering framework tailored for hardware design tasks, improving task-specific performance; 3) an end-to-end pipeline integrating specification review, RTL generation, and verification, reducing manual intervention; 4) specialized fine-tuning strategies, including domain adaptation and reinforcement learning, to enhance relevance and robustness. These innovations collectively enable models to handle complex, multi-faceted design data, achieve higher accuracy, and operate efficiently in industrial settings. The integration of hardware accelerators for inference further reduces latency and energy consumption, making deployment feasible at scale. Compared to prior rule-based or heuristic methods, these approaches offer scalable, flexible, and explainable AI solutions that can adapt to evolving design requirements.

• �� Data collection: Circuit descriptions, design specifications, images, and graphs from industry datasets (ISPD, DAC). • Model architecture: Multi-modal Transformer with separate encoders for text, images, and graphs, fused via attention mechanisms. • Pretraining: Large-scale unsupervised training on diverse circuit datasets to learn general semantic representations. • Fine-tuning: Task-specific supervised learning and reinforcement learning using labeled datasets for RTL generation, verification, and specification review. • Prompt engineering: Designing prompts to guide model outputs, including contextual cues and task-specific instructions. • Multi-modal fusion: Combining features from different data types to improve semantic understanding of complex circuits. • End-to-end pipeline: Automating from high-level specifications to RTL code, with integrated verification modules. • Hardware acceleration: Using GPUs/TPUs to optimize inference speed and energy efficiency, enabling industrial deployment.

The models were evaluated on benchmark datasets like ISPD and DAC, focusing on RTL code accuracy, verification success rate, and design time reduction. Baseline comparisons included rule-based algorithms and previous neural approaches. Hyperparameters such as model size (from 1B to 100B parameters), learning rate, and prompt design were systematically varied. Ablation studies assessed the contribution of multi-modal inputs and fine-tuning strategies. Industrial case studies demonstrated real-world applicability, measuring improvements in design cycle time and error rates. Cross-scenario tests validated robustness across different circuit types and complexity levels, ensuring generalization. Metrics included accuracy, F1-score, inference latency, and resource consumption, providing a comprehensive performance profile.

The largest models achieved RTL code accuracy exceeding 85%, outperforming traditional methods by 20%. The framework reduced design review time by 30%, and accelerator co-design speed increased 25-fold. Multi-modal fusion improved understanding of circuit semantics, especially in complex layouts. Prompt engineering further enhanced task-specific performance, with accuracy gains of 10-15%. Fine-tuning with domain data increased relevance and robustness, enabling reliable deployment in industrial environments. Ablation results confirmed that multi-modal inputs and tailored prompts are critical for optimal performance. Overall, the models demonstrated strong generalization, scalability, and efficiency, paving the way for AI-driven chip design automation.

Immediate applications include automated RTL code generation, chip specification review, and logic debugging, significantly reducing manual effort and errors. These models can be integrated into existing EDA tools to streamline workflows, especially in complex, multi-layered designs. Long-term, they can enable fully autonomous design pipelines, support rapid prototyping, and facilitate the development of AI-optimized hardware architectures. Industries such as semiconductor manufacturing, AI accelerators, and IoT device design stand to benefit immensely. Additionally, academia can leverage these models for research and education, fostering innovation in hardware-software co-design and multi-modal data integration.

Current models face challenges in handling extremely complex circuits with multi-layer dependencies, often resulting in reduced accuracy and increased inference time. The high computational and energy costs associated with large-scale models limit their deployment in resource-constrained environments. The lack of standardized benchmarks hampers cross-study comparisons, and interpretability remains limited, affecting trust in critical applications. Future work must focus on developing lightweight, explainable models, establishing industry standards, and improving multi-modal data fusion techniques to overcome these barriers and realize widespread industrial adoption.